1. Field of the Invention
The present invention relates to a semiconductor chip and a semiconductor device, and particularly relates to a plurality of semiconductor chips capable of being laminated and a semiconductor device composed of the lamination of these plural semiconductor chips. This is counterpart of and claims priority to Japanese Patent Application No. 372265/2003 filed on Oct. 31, 2003, which is herein incorporated by reference.
2. Description of the Related Art
With the aim of having a multifunctional semiconductor, a semiconductor chip laminated type package with a plurality of semiconductor chips laminated has been known.
As an example of such a semiconductor chip laminated type package, there is a stack type multichip package. The stack type multichip package is configured in such a manner that plural semiconductor chips are superimposed and mounted on a substrate and electrode pads of these semiconductor chips are connected to an electrical connection portion provided on the substrate by using a bonding wire, respectively.
In the stack type multichip package, with the aim of connecting the semiconductor chip to a circuit board electrically beyond a scope connectable by the wire bonding, it has been known that an electrode pad for relaying is provided in advance to relay an electrode pad of one semiconductor chip to an electrode pad of the other semiconductor chip (for example, refer to Patent Document 1).
In addition, with the aim of improving productivity of the semiconductor chip laminated type package, it has been known that plural semiconductor chips having the same configurations and the same functions are laminated with slightly deviated so that the electrode pads of respective semiconductor chips are arranged with deviated (for example, refer to Patent Document 2).
Further, in order to laminate two semiconductor chips, of which outer sizes and arrangements of the bonding pads are different, it has been known that a wiring sheet with a wire formed on its front surface is clipped between two semiconductor chips (for example, refer to Patent Document 3).
In addition, upon laminating a plurality of semiconductor chips, it has been known that the electrode pad of the semiconductor chip to be arranged at the lower side is formed larger than the normal electrode pad and it is formed in a long rectangular shape along an edge of the semiconductor chip (for example, refer to Patent Document 4).
To this larger formed electrode pad, a bonding wire to be connected to the electrode pad of the semiconductor chip arranged at the upper side, and a bonding wire to be connected to the electrode pad formed on an insulative substrate arranged further lower of the lower arranged semiconductor chip are connected.    [Patent Document 1] JP-A-2001-196529    [Patent Document 2] JP-A-2001-298150    [Patent Document 3] JP-A-2001-7278    [Patent Document 4] JP-A-2002-110898
The electrode pads disclosed in the above-described patent document 1 and patent document 4 are elongated and arranged along the edge of the semiconductor chip, and this results in limitation of the number of the electrode pads to be formed on the semiconductor chip.
According to the configuration of the patent document 2, leads and a plurality of semiconductor chips are directly connected with each other by wires. Accordingly, each wire is made longer and it is feared that short circuit and breaking of the wires each other may occur due to wire sweep.
According to the configuration of the patent document 3, a wiring sheet must be prepared separately, so that a process to clip this wiring sheet is required.
In the conventional semiconductor chip laminated type package with the same functional and same structural semiconductor chips laminated, the electrode pad of the semiconductor chip located at the upper side is directly connected to the substrate by the bonding wire. Accordingly, it may be feared that the short circuit and the breaking of the bonding wires one another may occur due to so-called wire sweep and this leads to malfunction of the device.
In addition, in order to prevent the short circuit of the bonding wires one another, the lengths of the bonding wires are made different each other in a height direction of the package so as to avoid contact of the plural bonding wires one another three-dimensionally. However, such a configuration may increase the thickness of the package.